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myson technology MTV112M (rev 2.0) 8051 embedded crt monitor controller flash version this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. revision 2.0 - 1 - 2001/05/18 features l 8051 core. l 384 -bytes internal ram. l 32k-bytes program flash rom. l 14-channels 5v open-drain pwm dac, 10 dedicated channels and 4 channels shared with i/o pin. l 28 bi-direction i/o pin ,12 dedicated pin,12 shared with dac, 4 shared with ddc/iic interface. l 3-output pin shared with h/v sync output and self test output pins. l sync processor for composite separation, polarity and frequency check, and polarity adjustment. l built-in monitor self-test pattern generator. l built-in low power reset circuit. l one slave mode iic interface and o ne master mode iic interface. l iic interface for ddc1/ddc2b and eeprom, only one eeprom needed to store ddc1/ddc2b and display mode information. l dual 4-bit adc or 4 channel 6-bit adc. l watchdog timer with programmable interval. l 40-pin pdip and 44 - pin plcc package. general description the MTV112M micro-controller is an 8051 cpu core embedded device specially tailored to crt monitor applications. it includes an 8051 cpu core, 384 -byte sram, 14 built-in pwm dacs, ddc1/ddc2b interface, 24cxx series eeprom interface, a/d converter and a 32k bytes internal program flash rom. block diagram xfr 8051 core p1.0-7 x1 x2 p2.0-3 p3.0-p3.2 p3.4 p0.0-7 rd wr int 1 rst p2.4-7 rd wr p0.0-7 watch-dog timer rst h / vsync control hsync vsync hblank vblank stout 14 channel pwm dac ddc 1/2 b & fifo interface hscl hsda iic interface isda iscl da10-13 da0-9 adc ad0 ad1 4 .com u datasheet
myson technology MTV112M (rev 2.0) revision 2.0 - 2 - 2001/05/18 1.0 pin connection MTV112M nc p1.5/ad3 p1.6/ad0 p1.7/ad1 reset hscl/p3.0/rxd hsda/p3.1/txd isda/p3.2/int0 hsync iscl/p3.4/t0 vsync da4/p5.4 da5/p5.5 da6/p5.6 da7/p5.7 da8 da9 stout/p4.2 da10/p2.7 da11/p2.6 da12/p2.5 nc nc hblank/p4.1 vblank/p4.0 x2 x1 vss p2.0/int0 p2.1 p2.2 p2.3 da13/p2.4 p1.4/ad2 p1.3/hclamp p1.2/halfh p1.1/halfv p1.0 vdd da0/p5.0 da1/p5.1 da2/p5.2 da3/p5.3 nc 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 MTV112M p1.0 p1.1/halfv p1.2/halfh p1.3/hclamp p1.4/ad2 p1.5/ad3 p1.6/ad0 p1.7/ad1 rst hscl/p3.0/rxd hsda/p3.1/txd isda/p3.2/int0 hsync iscl/p3.4/t0 vsync hblank/p4.1 vblank/p4.0 x2 x1 vss vdd da0/p5.0 da1/p5.1 da2/p5.2 da3/p5.3 da4/p5.4 da5/p5.5 da6/p5.6 da7/p5.7 da8 da9 stout/p4.2 da10/p2.7 da11/p2.6 da12/p2.5 da13/p2.4 p2.3 p2.2 p2.1 p2.0/int0 MTV112M p1.0 p1.1/halfv p1.2/halfh p1.3/hclamp p1.4/ad2 p1.5/ad3 p1.6/ad0 p1.7/ad1 rst hscl/p3.0/rxd hsda/p3.1/txd isda/p3.2/int0 hsync iscl/p3.4/t0 vsync nc hblank/p4.1 vblank/p4.0 x2 x1 vss vdd da0/p5.0 da1/p5.1 da2/p5.2 da3/p5.3 da4/p5.4 da5/p5.5 da6/p5.6 da7/p5.7 da8 da9 nc stout/p4.2 da10/p2.7 da11/p2.6 da12/p2.5 da13/p2.4 p2.3 p2.2 p2.1 p2.0/int0 4 .com u datasheet
myson technology MTV112M (rev 2.0) revision 2.0 - 3 - 2001/05/18 2.0 pin descriptions pin# name type 40 42 44 description p1.0 i/o 1 1 2 general purpose i/o p1.1/halfv i/o 2 2 3 general purpose i/o / vsync half frequency output. p1.2/halfh i/o 3 3 4 general purpose i/o / hsync half frequency output. p1.3/hclamp i/o 4 4 5 general purpose i/o / hsync clamp pulse output. p1.4/ad2 i/o 5 5 6 general purpose i/o / adc input. p1.5/ad3 i/o 6 6 8 general purpose i/o / adc input. p1.6/ad0 i/o 7 7 9 general purpose i/o / adc input p1.7/ad1 i/o 8 8 10 general purpose i/o / adc input rst i 9 9 11 active high reset hscl/p3.0/rxd i/o 10 10 12 iic clock / general purpose i/o / rxd hsda/p3.1/txd i/o 11 11 13 iic data / general purpose i/o / txd isda/p3.2/int0 i/o 12 12 14 iic data / general purpose i/o / int0 hsync i 13 13 15 horizontal sync or composite sync iscl/p3.4/t0 i/o 14 14 16 iic clock / general purpose i/o / t0 vsync i 15 15 17 vertical sync hblank/p4.1 o 16 17 19 horizontal blank / general purpose output vblank/p4.0 o 17 18 20 vertical blank / general purpose output x2 o 18 19 21 oscillator output x1 i 19 20 22 oscillator input vss - 20 21 23 ground p2.0/int0 i/o 21 22 24 general purpose i/o / int0 p2.1 i/o 22 23 25 general purpose i/o p2.2 i/o 23 24 26 general purpose i/o p2.3 i/o 24 25 27 general purpose i/o da13/p2.4 i/o 25 26 28 pwm dac output / general purpose i/o (open-drain) da12/p2.5 i/o 26 27 30 pwm dac output / general purpose i/o (open-drain) da11/p2.6 i/o 27 28 31 pwm dac output / general purpose i/o (open-drain) da10/p2.7 i/o 28 29 32 pwm dac output / general purpose i/o (open-drain) stout/p4.2 o 29 30 33 self-test video output / general purpose output da9 o 30 32 34 pwm dac output / general purpose i/o (open-drain) da8 o 31 33 35 pwm dac output / general purpose i/o (open-drain) da7/p5.7 o 32 34 36 pwm dac output / general purpose i/o (open-drain) da6/p5.6 o 33 35 37 pwm dac output / general purpose i/o (open-drain) da5/p5.5 o 34 36 38 pwm dac output / general purpose i/o (open-drain) da4/p5.4 o 35 37 39 pwm dac output / general purpose i/o (open-drain) da3/p5.3 o 36 38 41 pwm dac output / general purpose i/o (open-drain) da2/p5.2 o 37 39 42 pwm dac output / general purpose i/o (open-drain) da1/p5.1 o 38 40 43 pwm dac output / general purpose i/o (open-drain) da0/p5.0 o 39 41 44 pwm dac output / general purpose i/o (open-drain) vdd - 40 42 1 positive power supply 4 .com u datasheet
myson technology MTV112M (rev 2.0) revision 2.0 - 4 - 2001/05/18 3.0 functional description 1. 8051 cpu core MTV112M includes all 8051 functions with the following exceptions: 1.1 psen, ale, rd and wr pins are disabled. the external ram access is restricted to xfrs within MTV112M. 1.2 port 0, port 3.3, and ports 3.5 ~ 3.7 are not general-purpose i/o ports. they are dedicated to monitor control or dac pins. 1.3 int1 and t1 input pins are not provided. 1.4 ports 2.4 ~ 2.7 are shared with dac pins; ports 3.0 ~ 3.2, and port3.4 are shared with monitor control pins. in addition, there are 2 timers, 5 interrupt sources and a serial interface compatible with the standard 8051. the txd/ rxd (p3.0/p3.1) pins are shared with ddc interface. int0/t0 pins are shared with iic interface. an extra option can be used to switch the int0 source from p3.2 to p2.0. this feature maintains an external interrupt source when iic interface is enabled. note: all registers listed in this document reside in the external ram area (xfr). for the internal ram memory map please refer to the 8051 spec. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 padmod 30h (w) sint0 iicf ddce iice da13e da12e da11e da10e padmod 31h (w) p57e p56e p55e p54e p53e p52e p51e p50e padmod 37h (w) - - - - - - - more sint0 = 1 ? int0 source is pin #21. = 0 ? int0 source is pin #12. iicf = 1 ? select s 400khz master iic speed. = 0 ? select s 100khz master iic speed. ddce = 1 ? pin #10 is hscl; pin #11 is hsda. = 0 ? pin #10 is p3.0/rxd; pin #11 is p3.1/txd. iice = 1 ? pin #12 is isda; pin #14 is iscl. = 0 ? pin #12 is p3.2/(int0*); pin #14 is p3.4/t0. da13e = 1 ? pin #25 is da13. = 0 ? pin #25 is p2.4. da12e = 1 ? pin #26 is da12. = 0 ? pin #26 is p2.5. da11e = 1 ? pin #27 is da11. = 0 ? pin #27 is p2.6. da10e = 1 ? pin #28 is da10. = 0 ? pin #28 is p2.7. p5 7e = 1 ? pin #32 is p5.7. = 0 ? pin #32 is da7. p56e = 1 ? pin #33 is p5.6. ? = 0 ? pin #33 is da6. p55e = 1 ? pin #34 is p5.5. = 0 ? pin #34 is da5. p54e = 1 ? pin #35 is p5.4. = 0 ? pin #35 is da4. p53e = 1 ? pin #36 is p5.3. = 0 ? pin #36 is da3. p52e = 1 ? pin #37 is p5.2. 4 .com u datasheet
myson technology MTV112M (rev 2.0) revision 2.0 - 5 - 2001/05/18 = 0 ? pin #37 is da2. p51e = 1 ? pin #38 is p5.1. = 0 ? pin #38 is da1. p50e = 1 ? pin #39 is p5.0. = 0 ? pin #39 is da0. more = 1 ? bits p57e,p56e,p55e,p54e,p53e,p52e,p51e,p50e,dack,ehalfv, ehalfh ,enclp,adcmod can be programmed,and master iic speed is controlled by (mclk1,mclk0) bits. = 0 ? above bits internal keep ? 0 ? by MTV112M, and master iic speed is controlled by iicf bit. * sint0 should be 0 in this case. 2. memory allocation 2.1 internal special function registers ( sfr) sfr is a group of registers that is the same as standard 8051. 2.2 internal ram there is a 384 bytes ram in MTV112M. the first portion of the ram area con tains 256 bytes, accessible by setting psw.1=0 ; the second portion of the ram area contains 128 bytes, accessible by setting psw.1=1. 2.3 external special function registers (xfr) xfr is a group of registers allocated in the 8051 external ram area. most of the registers are used for monitor control or pwm dac. the program can initialize ri value and use "movx" instruction to access these registers. 3. pwm dac each d/a converter's output pulse width is controlled by an 8-bit register in xfr. the frequency of pwm clk is x ? tal or 2 * x ? tal, selected by dack. and the frequency of these dac outputs is (pwm clk frequency)/253 or (pwm clk frequency)/256, selected by div253. if div253=1, writing fdh/feh/ffh to the dac register generates stable high output. if div253=0, the output will pulse low at least once even if the dac register's content is ffh. writing 00h to the dac register generates stable low output. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 da0 20h (r/w) da0 b7 da0 b6 da0 b5 da0 b4 da0 b3 da0 b2 da0 b1 da0 b0 da1 21h (r/w) da1 b7 da1 b6 da1 b5 da1 b4 da1 b3 da1 b2 da1 b1 da1 b0 accessible by indirect addressing only. the value of psw.1 = both 0 and 1. (using mov a, @ri instruction) ffh 80h 7fh 00h sfr accessible by direct addressing. accessible by direct and indirect addressing. psw.1=0 accessible by direct and indirect addressing. psw.1 =1 xfr accessible by indirect external ram addressing. (using movx a, @ri instruction.) ffh 00h 4 .com u datasheet
myson technology MTV112M (rev 2.0) revision 2.0 - 6 - 2001/05/18 da2 22h (r/w) da2 b7 da2 b6 da2 b5 da2 b4 da2 b3 da2 b2 da2 b1 da2 b0 da3 23h (r/w) da3 b7 da3 b6 da3 b5 da3 b4 da3 b3 da3 b2 da3 b1 da3 b0 da4 24h (r/w) da4 b7 da4 b6 da4 b5 da4 b4 da4 b3 da4 b2 da4 b1 da4 b0 da5 25h (r/w) da5 b7 da5 b6 da5 b5 da5 b4 da5 b3 da5 b2 da5 b1 da5 b0 da6 26h (r/w) da6 b7 da6 b6 da6 b5 da6 b4 da6 b3 da6 b2 da6 b1 da6 b0 da7 27h (r/w) da7 b7 da7 b6 da7 b5 da7 b4 da7 b3 da7 b2 da7 b1 da7 b0 da8 28h (r/w) da8 b7 da8 b6 da8 b5 da8 b4 da8 b3 da8 b2 da8 b1 da8 b0 da9 29h (r/w) da9 b7 da9 b6 da9 b5 da9 b4 da9 b3 da9 b2 da9 b1 da9 b0 da10 2ah (r/w) da10 b7 da10 b6 da10 b5 da10 b4 da10 b3 da10 b2 da10 b1 da10 b0 da11 2bh (r/w) da11 b7 da11 b6 da11 b5 da11 b4 da11 b3 da11 b2 da11 b1 da11 b0 da12 2ch (r/w) da12 b7 da12 b6 da12 b5 da12 b4 da12 b3 da12 b2 da12 b1 da12 b0 da13 2dh (r/w) da13 b7 da13 b6 da13 b5 da13 b4 da13 b3 da13 b2 da13 b1 da13 b0 wdt 80h wen wclr clrddc div253 dack wdt2 wdt1 wdt0 da0 (r/w ) : the output pulse width control for da0. da1 (r/w ) : the output pulse width control for da1. da2 (r/w ) : the output pulse width c ontrol for da2. da3 (r/w ) : the output pulse width control for da3. da4 (r/w ) : the output pulse width control for da4. da5 (r/w ) : the output pulse width control for da5. da6 (r/w ) : the output pulse width control for da6. da7 (r/w ) : the output pulse wid th control for da7. da8 (r/w ) : the output pulse width control for da8. da9 (r/w ) : the output pulse width control for da9. da10 (r/w ) : the output pulse width control for da10. da11 (r/w ) : the output pulse width control for da11. da12 (r/w ) : the output pulse width control for da12. da13 (r/w ) : the output pulse width control for da13. wdt (w ) : watchdog timer & special control bit. div253 = 1 ? the pwm dac outputs frequency is (pwm clk frequency)/253. = 0 ? the pwm dac output frequency is xtal frequency/256. dack = 1 ? the pwm clk frequency is 2 x ( x ? tal frequency). = 0 ? the pwm clk frequency is ( x ? tal frequency). *1. all d/a converters are centered with value 80h after power-on. 4. h/v sync processing the h/v sync processing block performs the functions of composite signal separation, sync input presence check, frequency counting, and polarity detection and control, as well as the protection of vblank output while vsync speeds up to a high ddc communication clock rate. the present and frequency function block treat any pulse less than one osc period as noise. 4.1 composite sync separation MTV112M continuously monitors the input hsync. if the vertical sync pulse can be extracted from the input, a cvpre flag is set and the user can select the extracted "cvsync" for the source of polarity check, frequency count and vblank. the cvsync will have a 10-16 us delay compared to the original signal. the delay depends on the osc frequency and composite mix method. 4.2 h/v frequency counter MTV112M can discriminate hsync/vsync frequency and saves the information in xfrs. the 15-bit hcounter counts the time of the 64xhsync period, but only 11 upper bits are loaded into the 4 .com u datasheet
myson technology MTV112M (rev 2.0) revision 2.0 - 7 - 2001/05/18 hcnth/hcntl latch. the 11-bit output value is {2/h-freq} / {1/osc-freq}, updated once per vsync/cvsync period when vsync/cvsync is present or continuously updated when vsync/cvsync is not present. the 14-bit vcounter counts the time between 2 vsync pulses, but only 9 upper bits are loaded into the vcnth/vcntl latch. the 9-bit output value is {1/v-freq} / {512/osc-freq }, updated every vsync/cvsync period. an extra overflow bit indicates the condition of the h/v counter overflow. the vfchg/ hfchg interrupt is active when vcnt/hcnt value changes or overflows. tables 4.2.1 and 4.2.2 shows the hcnt/vcnt value under the operations of 8mhz and 12mhz . 4.2.1 h- freq table output value (11 bits) h- freq( khz) 8mhz osc (hex / dec) 12mhz osc (hex / dec) 1 30 215h / 533 320h / 800 2 31.5 1fbh / 507 2f9h / 761 3 33.5 1ddh /477 2cch / 716 4 35.5 1c2h / 450 2a4h / 676 5 36.8 1b2h / 434 28ch / 652 6 38 1a5h / 421 277h / 631 7 40 190h / 400 258h / 600 8 48 14dh / 333 1f4h / 500 9 50 140h / 320 1e0h / 480 10 57 118h / 280 1a5h / 421 11 60 10ah / 266 190h / 400 12 64 0fah / 250 177h / 375 13 100 0a0h / 160 0f0h / 240 *1. the h- freq output (hf10 - hf0) is valid. *2. the tolerance deviation is + 1 lsb. 4.2.2 v- freq table output value (9 bits) v- freq(hz) 8mhz osc (hex / dec) 12mhz osc (hex / dec) 1 56.25 115h / 277 1a0h / 416 2 59.94 104h / 260 187h / 391 3 60 104h / 260 186h / 390 4 60.32 103h / 259 184h / 388 5 60.53 102h / 258 183h / 387 6 66.67 0eah / 234 15fh / 351 7 70.069 0deh / 222 14eh / 334 8 70.08 0deh / 222 14eh / 334 9 72 0d9h /217 145h / 325 10 72.378 0d7h / 215 143h / 323 11 72.7 0d6h / 214 142h / 322 12 87 0b3h / 179 10dh / 269 *1. the v- freq output (vf8 - vf0) is valid. *2. the tolerance deviation is + 1 lsb. 4.3 h/v presence check the hpresent function checks the input hsync pulse. the hpre flag is set when hsync is over 10khz or cleared when hsync is under 10hz. the vpresent function checks the input vsync pulse. the vpre flag is set when vsync is over 40hz or cleared when vsync is under 10hz. a control bit "prefs" selects the time base for these functions. the hprchg interrupt is set when the hpre value changes. the vprchg 4 .com u datasheet
myson technology MTV112M (rev 2.0) revision 2.0 - 8 - 2001/05/18 interrupt is set when the vpre/ cvpre value changes. however, the cvpre flag interrupt may be disabled when s/w disables the composite function. 4.4 h/v polarity detection the polarity functions detect the input hsync/vsync high and low pulse duty cycle. if the high pulse duration is longer than that of the low pulse, the negative polarity is asserted; otherwise, positive polarity is asserted. the hplchg interrupt is set when the hpol value changes. the vplchg interrupt is set when the vpol value changes. 4.5 output hblank/vblank control and polarity adjustment the hblank is the mux output of hsync and self-test horizontal pattern. the vblank is the mux output of vsync, cvsync and the self-test vertical pattern. the mux selection and output polarity are s/w controllable. the vblank output is cut off when vsync frequency is over 200hz or 133hz depends on 8mhz/12mhz osc selection. the hblank/vblank shares the output pin with p4.1/ p4.0. 4.6 self-test pattern generator this generator can generate 4 display patterns for testing purposes: positive cross-hatch, negative cross- hatch, full white, and full black (shown in the following figure). it was originally designed to support the monitor manufacturer in performing a burn-in test, or to offer the end-user a reference to check the monitor. the generator's output stout shares the output pin with p4.2. display region positive c ross- h atch negative c ross-hatch full w hite full b lack 4 .com u datasheet
myson technology MTV112M (rev 2.0) revision 2.0 - 9 - 2001/05/18 MTV112M self-test p attern timing (8mhz) 63.5khz, 60hz 31.7khz, 60hz absolute time h dots absolute time h dots hor. total t ime us(a)=15.75 1280 us(a)=31.5 640 hor. acitve time us(d)=12.05 979.3 us(d)=24.05 488.6 hor. f. p. us(e)=0.2 16.25 us(e)=0.45 9 sync pulse width us(b)=1.5 122 us(b)=3 61 hor. b. p. us(c)=2 162.54 us(c)=4 81.27 v lines v lines hor. total t ime us(o)=16.6635 1024 us(o)=16.6635 480 hor. active time us(r)=15.6555 962 us(r)=15.6555 451 hor. f. p. us(s)=0.063 3.87 us(s)=0.063 1.82 sync pulse width us(p)=0.063 3.87 us(p)=0.063 1.82 hor. b. p. us(q)=0.882 54.2 us(q)=0.882 25.4 * 8 x 8 blocks of cross - hatch pattern in display region. 4.7 vsync interrupt MTV112M check s the vsync input pulse and generate s an interrupt at its leading edge. the vsync1 flag is set each time MTV112M detects a vsync pulse. 4. 8 h/v sync processor register reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pstus 40h (r) cvpre x hpol vpol hpre vpre hoff voff hcnth 41h (r) hovf x x x x hf10 hf9 hf8 hcntl 42h (r) hf7 hf6 hf5 hf4 hf3 hf2 hf1 hf0 vcnth 43h (r) vovf x x x x x x vf8 vcntl 44h (r) vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 pctr0 40h (w) c1 c0 hvsel stosel prefs halfv hbpl vbpl pctr2 42h (w) x x x selft st bsh rt1 rt0 stf pctr3 43h (w) enclp clpeg clppo clpw2 clpw1 clpw0 ehalfv ehalfh p4out 44h (w) x x x x x p42 p41 p40 d c b a e r q p o s hor. vert. 4 .com u datasheet
myson technology MTV112M (rev 2.0) revision 2.0 - 10 - 2001/05/18 p5out 45h (r/w) p57 p56 p55 p54 p53 p52 p51 p50 intflg 50h (r/w) hprchg vprchg hplchg vplchg hfchg vfchg fifoi mi inten 60h (w) ehpr evpr ehpl evpl ehf evf efifo emi intflg 51h(r/w) x x x x x x x vsync inten 61h(w) x x x x x x x evsi present check digital filter present check vpre frequency count vfreq polarity check vpol high frequency mask vself cvsync polarity check & sync seperator cvpre hpol hself digital filter present check & frequency count hpre hfreq hbpl vbpl vblank hblank vsync hsync h/v sync processor block diagram pstus (r ) : the status of polarity, presence and static level for hsync and vsync. cvpre = 1 ? the extracted cvsync is present. = 0 ? the extracted cvsync is not present. h pol = 1 ? hsync input is positive polarity. = 0 ? hsync input is negative polarity. v pol = 1 ? vsync (cvsync) is positive polarity. = 0 ? vsync (cvsync) is negative polarity. h pre = 1 ? hsync input is present. = 0 ? hsync input is not present. v pre = 1 ? vsync input is present. = 0 ? vsync input is not present. h off* = 1 ? hsync input's off-level is high. = 0 ? hsync input's off-level is low. v off* = 1 ? vsync input's off-level is high. = 0 ? vsync input's off-level is low. *h off and v off are valid when h pre=0 or v pre=0. hcnth (r ) : h- freq counter's high bits. hovf = 1 ? h- freq counter overflows; this bit is cleared by h/w when condition removed. hf10 - hf8 : 3 high bits of h- freq counter. hcntl (r ) : h- freq counter's low bits. 4 .com u datasheet
myson technology MTV112M (rev 2.0) revision 2.0 - 11 - 2001/05/18 vcnth (r ) : v- freq counter's high bits. vovf = 1 ? v- freq counter overflows; this bit is cleared by h/w when condition removed. vf8 : high bit of v- freq counter. vcntl (r ) : v- freq counter's low bits. pctr0 (w ) : sync processor control register 0. c1, c0 = 1,1 ? selects cvsync as the polarity, freq and vblank source. = 1,0 ? selects vsync as the polarity, freq and vblank source. = 0,0 ? disables composite function (mtv012 compatible mode). = 0,1 ? h/w auto switches to cvsync when cvpre=1 and vspre=0. hvsel = 1 ? pin #16 is p4 . 1, pin #17 is p4 . 0. = 0 ? pin #16 is hblank, pin #17 is vblank. stosel = 1 ? pin #29 is p4 . 2. = 0 ? pin #29 is stout. prefs = 0 ? selects 8mhz osc as h/v presence check and self-test pattern time base. = 1 ? selects 12mhz osc as h/v presence check and self-test pattern time base. halfv = 1 ? vblank is half frequency output of vsync. hb pl = 1 ? negative polarity hblank output. = 0 ? positive polarity hblank output. vb pl = 1 ? negative polarity vblank output. = 0 ? positive polarity vblank output. pctr2 (w ) : self-test pattern generator control. s elft = 1 ? enables generator. = 0 ? disables generator. st bsh = 1 ? 63.5khz (horizontal) output selected. = 0 ? 31.75khz (horizontal) output selected. rt1, rt0= 0,0 ? positive cross-hatch pattern output. = 0,1 ? negative cross-hatch pattern output. = 1,0 ? full white pattern output. = 1,1 ? full black pattern output. stf = 1 ? enables stout output. = 0 ? disables stout output. pctr3 (w ) : hsync clamp pulse control register. enclp = 1 ? pin #4 is hclamp. = 0 ? pin #4 is p1.3. clpeg = 1 ? clamp pulse follows hsync leading edge. = 0 ? clamp pulse follows hsync trailing edge. clppo = 1 ? positive polarity clamp pulse output. = 0 ? negative polarity clamp pulse output. clpw2 : clpw0 : pulse width of clamp pulse is [(clpw2 :clpw0) + 1] x 0.25 s for 8mhz x ? tal selection,or [(clpw2 :clpw0) + 1] x 0.167 s for 12mhz x ? tal selection. ehalfv= 1 ? pin #2 is halfv. = 0 ? pin #2 is p1.1. ehalfv= 1 ? pin #3 is halfh. = 0 ? pin #3 is p1.2. p4out (w ) : port 4 data output value. p5out (r/w ) : port 5 data input/output value. 4 .com u datasheet
myson technology MTV112M (rev 2.0) revision 2.0 - 12 - 2001/05/18 intflg (w ) : interrupt flag. an interrupt event will set its individual flag, and, if the corresponding interrupt enabler bit is set, the 8051 core's int1 source will be driven by a zero level. software must clear this register while serving the interrupt routine. hprchg= 1 ? no action. = 0 ? clears hsync presence change flag. vprchg= 1 ? no action. = 0 ? clears vsync presence change flag. hplchg = 1 ? no action. = 0 ? clears hsync polarity change flag. vplchg = 1 ? no action. = 0 ? clears vsync polarity change flag. hfchg = 1 ? no action. = 0 ? clears hsync frequency change flag. vfchg = 1 ? no action. = 0 ? clears vsync frequency change flag. vsynci= 1 ? no action. = 0 ? clear s vsync interrupt flag. intflg (r ) : interrupt flag. hprchg= 1 ? indicates an hsync presence change. vprchg= 1 ? indicates a vsync presence change. hplchg = 1 ? indicates a hsync polarity change. vplchg = 1 ? indicates a vsync polarity change. hfchg = 1 ? indicates an hsync frequency change or counter overflow. vfchg = 1 ? indicates a vsync frequency change or counter overflow. vsynci= 1 ? indicates a vsync interrupt. inten (w ) : interrupt enabler. ehpr = 1 ? enables hsync presence change interrupt. evpr = 1 ? enables vsync presence change interrupt. ehpl = 1 ? enables hsync polarity change interrupt. evpl = 1 ? enables vsync polarity change interrupt. ehf = 1 ? enables hsync frequency change / counter overflow interrupt. evf = 1 ? enables vsync frequency change / counter overflow interrupt. evsi = 1 ? enable s vsync interrupt. 5. ddc & iic interface 5.1 ddc1 mode MTV112M enters ddc1 mode after reset. in this mode, vsync is used as a data clock. the hscl pin should remain at high. the data output to the hsda pin is taken from 8 bytes fifo in MTV112M. MTV112M fetches the data byte from fifo, then sends it in a 9-bit packet format which includes a null bit (=1) as packet separator. the software program should load edid data (original stored in eeprom) into fifo and take care of the fifo depth. fifo sets the fifoi (fifo low interrupt) flag when there are fewer than n (n=2,3,4 or 5 controlled by ls1, ls0) bytes to be output to the hsda pin. to prevent fifo from emptying, software needs to write edid data to fifo as soon as fifoi is set. on the other hand, fifo sets the fifoh flag when its capacity is full. software should not write additional data to fifo in such instance. the fifoi interrupt can be masked or enabled by an efifo control bit. a simple way to control fifo is to set (ls1, ls0=1,0) and enable fifoi interrupt, then software may load 4 bytes into fifo each time a fifoi interrupt arises. a special control bit "ldfifo" can reduce the software effort when edid data is stored in eeprom. if ldfifo=1, fifo will be automatically loaded with mbuf data when software reads mbuf xfr. 4 .com u datasheet
myson technology MTV112M (rev 2.0) revision 2.0 - 13 - 2001/05/18 5.2 ddc2b mode MTV112M switches to ddc2b mode when it detects a high to low transition on the hscl pin. once MTV112M enters ddc2b mode, the host can access the eeprom using iic bus protocol as if the hsda and hscl are directly bypassed to isda and iscl pins. MTV112M will return to ddc1 mode if hscl is kept high for a 128 vsync clock period. however, it will lock in ddc2b mode if a valid iic access has been detected on hscl/hsda bus. the ddc2 flag reflects the current ddc status. s/w may clear it by setting clrddc. control bits m128/m256 are used to block the eeprom write operation from the host if the address is over 128/256. 5.3 master mode iic function block the master mode iic block is connected to the isda and iscl pins. its speed can be selected to 100khz or 400khz by s/w set iicf control bit while more=0, or to 50khz ,100khz,200khz or 400khz by s/w set (mclk1,mclk0) bits while more=1 . the software program can access the external eeprom through this interface. since the edid/vdif data and display information share the common eeprom, precaution must be taken to avoid bus conflict. in ddc1 mode, the iic interface is controlled by MTV112M only. in ddc2b mode, the host may access the eeprom directly. software can test the hscl condition by reading the busy flag, which is set in case hscl=0. a summary of master iic access is illustrated as follows: 5.3.1. to write eeprom 1. write the eeprom slave address to mbuf (bit 0 = 0). 2. set the s bit to start. 3. after MTV112M transmits this byte, an mi interrupt will be triggered. 4. the program can write mbuf to transfer the next byte or set the p bit to stop. * please see the attachments about "master iic transmission timing". 5.3.2. to read eeprom 1. write the slave address to mbuf (bit 0 = 1). 2. set the s bit to start. 3. after MTV112M transmits this byte, a mi interrupt will be triggered. 4. set or reset the ack flag according to the iic protocol. 5. read out the useless byte to mbuf to continue the data transfer. 6. after MTV112M receives a new byte, the mi interrupt is triggered again. 7. reading mbuf also triggers the next receiving operation, but setting the p bit before reading can terminate the operation. * please see the attachments about "master iic timing receiving". 5.4 slave mode iic function block the slave mode iic block can be connected to hsda/hscl or isda/iscl pins, and selected by the slvsel control bit. this block can receive/transmit data using the iic protocol. s/w may set the slvadr register to determine which slave address the block should respond to. in receiving mode, the block first detects an iic slave address match condition then issues a slvmi interrupt. the data received from sda is shifted into a shift register and written to the rcbuf latch. the first byte loaded is the word address (slave address is dropped). this block also generates an rcbi (receive buffer full interrupt) each time the rcbuf is loaded. if s/w can't read out the rcbuf in time, the next byte will not be written to rcbuf and the slave block will return nack to the master. this feature guarantees the data integrity of communication. a wadr flag can tell s/w if the data in rcbuf is a word address. in transmission mode, the block first detects an iic slave address match condition then issues a slvmi. in the meantime, the data pre-stored in the txbuf is loaded into the shift register, results in txbuf emptying and generates a txbi (transmission buffer interrupt). s/w should write the txbuf a new byte for the next transfer before the shift register empties. failure to do this will cause data corruption. the txbi occurs each time the shift register receives new data from txbuf. the slvmi is cleared by writing the slvstus register. the rcbi is cleared by reading the rcbuf. the txbi is cleared by writing the txbuf. if the control bit enscl is set, the block will hold scl low until the rcbi/txbi is cleared. *please see the attachments about "slave iic block timing". 4 .com u datasheet
myson technology MTV112M (rev 2.0) revision 2.0 - 14 - 2001/05/18 reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 mctr 00h (w) ls1 ls0 ldfifo m256 m128 ack p s mstus 00h (r) x sclerr ddc2 berr hfreq fifoh fifol busy mctr 01h (w) x x x x x x mclk1 mclk0 mbuf 10h (r/w) mbuf7 mbuf6 mbuf5 mbuf4 mbuf3 mbuf2 mbuf1 mbuf0 intflg 50h (r/w) hprchg vprchg hplchg vplchg hfchg vfchg fifoi mi inten 60h (w) ehpr evpr ehpl evpl ehf evf efifo emi fifo 70h (w) fifo7 fifo6 fifo5 fifo4 fifo3 fifo2 fifo1 fifo0 slvctr 90h (w) enslv slvsel ercbi eslvmi etxbi enscl x x slvstus 91h (r) wadr slvs rcbi slvmi txbi rwb ackin x slvstus 91h (w) write to clear slvmi rcbuf 92h (r) rcbuf7 rcbuf6 rcbuf5 rcbuf4 rcbuf3 rcbuf2 rcbuf1 rcbuf0 txbuf 92h (w) txbuf7 txbuf6 txbuf5 txbuf4 txbuf3 txbuf2 txbuf1 txbuf0 slvadr 93h (w) slvadr7 slvadr6 slvadr5 slvadr4 slvadr3 slvadr2 slvadr1 x mctr (w ) : master iic interface control register. ls1, ls0 = 11 ? fifol is the status in which fifo depth < 5. = 10 ? fifol is the status in which fifo depth < 4. = 01 ? fifol is the status in which fifo depth < 3. = 00 ? fifol is the status in which fifo depth < 2. ldfifo = 1 ? fifo will be written while s/w reads mbuf. m25 6 = 1 ? disables host writing eeprom when address is over 256. m128 = 1 ? disables host writing eeprom when address is over 128. ack = 1 ? in receiving mode, no acknowledgment is given by MTV112M. = 0 ? in receiving mode, ack is returned by MTV112M. s, p = - , 0 ? start condition when master iic is not transferring. = x, - ? stop condition when master iic is not transferring. = 1, x ? will resume transfer after a read/write mbuf operation. = x, 0 ? forces hscl low and occupies the iic bus. mclk1 : mclk0 : master iic speed select, = 0 ? 50khz for 8mhz x ? tal, 75khz for 12mhz x ? tal. = 1 ? 100khz for 8mhz x ? tal, 150khz for 12mhz x ? tal. = 2 ? 200 khz for 8mhz x ? tal, 300khz for 12mhz x ? tal . = 3 ? 400 khz for 8mhz x ? tal, 600khz for 12mhz x ? tal. * MTV112M uses a 100khz clock to sample the s/p bit; any pulse should sustain at least 20us. * a write/read mbuf operation can be recognized only after 10us of the mi flag's rising edge. mstus (r ) : master iic interface status r egister. sclerr = 1 ? the iscl pin has been pulled low by other devices during the transfer, cleared when s=0. ddc2 = 1 ? ddc2b is active. = 0 ? MTV112M remains in ddc1 mode. berr = 1 ? iic bus error, no ack received from the slave, updated each time the slave sends ack on the isda pin. hfreq = 1 ? MTV112M has detected a higher than 200hz clock on the vsync pin. fifoh = 1 ? fifo high indicated. fifol = 1 ? fifo low indicated. busy = 1 ? host drives the hscl pin to low. * while writing fifo, the fifoh/fifol flag will reflect the fifo condition after 30us. 4 .com u datasheet
myson technology MTV112M (rev 2.0) revision 2.0 - 15 - 2001/05/18 mbuf (w ) : master iic data shift register, after start and before stop condition, write this register will resume MTV112M's transmission to the iic bus. mbuf (r ) : master iic data shift re gister, after start and before stop condition, read this register will resume MTV112M's receiving from the iic bus. intflg (w ) : interrupt flag. an interrupt event will set its individual flag, and, if the corresponding interrupt enabler bit is set, the 8051 int1 source will be driven by a zero level. software must clear this register while serving the interrupt routine. fifoi = 1 ? no action. = 0 ? clears fifoi flag. mi = 1 ? no action. = 0 ? clears master iic bus interrupt flag (mi). intflg (r ) : interrupt flag. fifoi = 1 ? indicates the fifo low condition; when efifo is set, MTV112M will be interrupted by int1. mi = 1 ? indicates when a byte is sent/received to/from the iic bus; when eme is active, MTV112M will be interrupted by int1. inten (w ) : interrupt enabler. efifo = 1 ? enables fifo interrupt. emi = 1 ? enables master iic bus interrupt. fifo (w ) : writes fifo contents. slvctr (w ) : slave iic block control. enslv = 1 ? enables slave iic block. = 0 ? disables slave iic block. slvsel = 1 ? slave iic connects to isda/iscl. = 0 ? slave iic connects to hsda/hscl. ercbi = 1 ? enables slave receiving buffer interrupt. eslvmi = 1 ? enables slave address match interrupt. etxbi = 1 ? enables slave transmission buffer interrupt. enscl = 1 ? enables slave block to hold scl pin low. slvstus (r ) : slave iic block status. wadr = 1 ? the data in slvbuf is a word address. slvs = 1 ? the slave block has detected a start; cleared when stop detected. rcbi = 1 ? rcbuf has loaded a new data byte; reset by s/w reading rcbuf. slvmi = 1 ? the slave block has detected the slave address match condition; cleared by s/w writing slvstus. txbi = 1 ? txbuf is empty ; reset by s/w writing txbuf. rwb = 1 ? current transfer is slave transmitting. = 0 ? current transfer is slave receiving. ackin = 1 ? master responds to nack. slvstus (w ) : clears slvmi flag. rcbuf (r ) : slave iic receives data buffer. txbuf (w ) : slave iic transmits data buffer. slvadr (w ) : slave iic address to which the slave block should respond. 4 .com u datasheet
myson technology MTV112M (rev 2.0) revision 2.0 - 16 - 2001/05/18 6. low power reset (lvr) & watchdog timer when the voltage level of the power supply is below 4.0v for a specific time, the lvr will generate a chip resetting signal. after the power supply is above 4.0v, lvr maintains the reset state for 144 xtal cycles to guarantee the chip exit reset condition has a stable xtal oscillation. the specific time of power supply in a low level is 3us and is adjustable by an external capacitor connected to the rst pin. the watchdog timer automatically generates a device reset when it overflows. the interval of overflow is 0.25 sec x n, in which n is a number from 1 to 8, and can be programmed via register wdt (2:0). the timer function is disabled after power-on reset. the user can activate this function by setting wen and clear the timer by setting wclr. 7. a/d converter the mtv112 is equipped with two 4-bit or four 6-bit a/d converters. each one can be enabled/disabled by s/w control. the refresh rate for the adc is osc freq./6144(4-bit) or osc freq./12288(6-bit). the adc compare the input pin voltage with the internal vdd*n/16(4-bit) or vdd*n/64(6-bit) voltage (where n = 0 -15 or n = 0 - 63). the adc output value is n when pin voltage is greater than vdd*n/16 or vdd *n/64 and smaller than vdd*(n+1)/16 or vdd*(n+1)/64. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 adc a0h (w) enadc adcmod x x eadc3 eadc2 eadc1 eadc0 adc a0h (r) ad1b3 ad1b2 ad1b1 ad1b0 ad0b3 ad0b2 ad0b1 ad0b0 adc a0h (r) x x adb5 adb4 adb3 adb2 adb1 adb0 wdt 80h (w) wen wclr clrddc div253 dack wdt2 wdt1 wdt0 wdt (w ) : watchdog timer control register. wen = 1 ? enables watchdog timer. wclr = 1 ? clears watchdog timer. clrddc = 1 ? clears ddc2 flag. wdt2: wdt0 = 0 ? overflow interval = 8 x 0.25 sec. = 1 ? overflow interval = 1 x 0.25 sec. = 2 ? overflow interval = 2 x 0.25 sec. = 3 ? overflow interval = 3 x 0.25 sec. = 4 ? overflow interval = 4 x 0.25 sec. = 5 ? overflow interval = 5 x 0.25 sec. = 6 ? overflow interval = 6 x 0.25 sec. = 7 ? overflow interval = 7 x 0.25 sec. adc (w ) : adc control. enadc = 1 ? enables adc. adcmod = 1 ? 4 channels 6 bits adc are selected. note: only one adc input can be enabled at the same time. = 0 ? dual 4 bits adc are selected .(adc1 and adc0) eadc3 = 1 ? enables adc3 pin input. eadc2 = 1 ? enables adc2 pin input. eadc1 = 1 ? enables adc1 pin input. eadc0 = 1 ? enables adc0 pin input. adc (r ) : adc conversion result. ad1b3: ad1b0 4-bit adc1 convert result. ad0b3: ad0b0 4-bit adc0 convert result. adb5: adb0 6-bit adc convert result. 4 .com u datasheet
myson technology MTV112M (rev 2.0) revision 2.0 - 17 - 2001/05/18 4.0 test mode condition in normal applications, users should avoid the mtv012 entering its test/program mode, outlined as follow: test mode a: reset=1 & da9=1 & da8=0 & sto=0 test mode b: reset falling edge & da9=1 & da8=0 & sto=1 program mode: reset=1 & da9=0 & da8=1 5.0 electrical parameters 5.1 absolute maximum ratings at: ta= 0 to 70 o c, vss=0v name symbol range unit maximum supply voltage vdd -0.3 to +6.0 v maximum input voltage vin -0.3 to vdd+0.3 v maximum output voltage vout -0.3 to vdd+0.3 v maximum operating temperature topg 0 to +70 o c maximum storage temperature tstg -25 to +125 o c 5.2 allowable operating conditions at: ta= 0 to 70 o c, vss=0v name symbol min. max. unit supply voltage vdd 4.0 6.0 v input "h" voltage vih1 0.4 x vdd vdd +0.3 v input "l" voltage vil1 -0.3 0.2 x vdd v operating freq. fopg - 15 mhz 5.3 dc characteristics at: ta=0 to 70 o c, vdd=4.0v ~ 6.0v, vss=0v name symbol condition min. typ. max. unit output "h" voltage, except open- drain pins: pin #s 16, 17, 29 voh1 ioh=-50ua 4 v output "h" voltage, pin #s 16, 17, 29 voh2 ioh=-1ma 4 v output "l" voltage vol iol=8ma 0.45 v active 18 24 ma idle 1.3 4.0 ma power supply current idd power-down 50 80 ua rst pull-down resistor rrst vdd=5v 50 150 kohm pin capacitance cio 15 pf 5.4 ac characteristics at: ta=0 to 70 o c, vdd=4.0v ~ 6.0v, vss=0v name symbol condition min. typ. max. unit crystal frequency fxtal 8 mhz pwm dac frequency fda fxtal=8mhz 31.25 31.62 khz pwm dac frequency fda fxtal=12mhz 46.875 47.43 khz hs input pulse width thipw fxtal=8mhz 0.3 12 us vs input pulse width tvipw fxtal=8mhz 3 us 4 .com u datasheet
myson technology MTV112M (rev 2.0) revision 2.0 - 18 - 2001/05/18 36.83mm +/-0.05 15.494mm +/-0.254 70typ . 0.457mm +/-0.127 1.270mm +/-0.254 1.981mm +/-0.254 3.81mm +/-0.127 1.778mm +/-0.127 0.254mm (min.) 3.302mm +/-0.254 13.868mm +/-0.102 16.256mm +/-0.508 0.254mm +/-0.102 5 o ~7 0 6 o +/-3 o hs input pulse width thipw fxtal=12mhz 0.2 8 us vs input pulse width tvipw fxtal=12mhz 2 us hsync to hblank output jitter thhbj 5 ns h+v to vblank output delay tvvbd fxtal=8mhz 16 us h+v to vblank output delay tvvbd fxtal=12mhz 10 us vs pulse width in h+v signal tvcpw fxtal=8mhz 32 us vs pulse width in h+v signal tvcpw fxtal=12mhz 20 us 6.0 package dimension 6 . 1 40 pin pdip 600 mil 6 . 2 42 pin sdip 600 mil 52.197mm +/- 0.127 15.494mm +/- 0.254 2.540m m 0.457mm +/- 0.127 1.270mm +/- 0.254 1.981m m +/-0.254 3.81mm +/-0.127 1.778m m +/-0.127 0.254m m (min.) 3.302m m +/-0.254 13.868mm +/- 0.102 16.256mm +/- 0.508 0.254m m +/-0.102 5 o ~7 0 6 o +/- 3 o 4 .com u datasheet
myson technology MTV112M (rev 2.0) revision 2.0 - 19 - 2001/05/18 6 . 3 4 4 pin plcc unit: inch pin #1 hole 0.653 +/-0.003 0.690 +/-0.005 0.690 +/-0.005 0.653 +/-0.003 0.045*45 0 0.180 max. 0.020 min. 0.610 +/-0.02 0.500 0.070 0.070 7 0 typ. 0.010 0.050 typ. 0.013~0.021 typ. 0.026~0.032 typ. 4 .com u datasheet
myson technology MTV112M (rev 2.0) revision 2.0 - 20 - 2001/05/18 7 .0 ordering information standard configurations: prefix part type package type rom size (k) mtv 112m n: pdip s: sdip v: plcc 32 part numbers: prefix part type package type rom size (k) mtv 112m n 32 mtv 112m s 32 mtv 112m v 32 4 .com u datasheet

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